Monday, 8 July 2013

1timescale in Verilog


Delay unit is specified using 'timescale, which is declared as `timescale time_unit base / precision base 
--time_unit is the amount of time a delay of #1 represents. The time unit must be 1 10 or 100
 
--base is the time base for each unit, ranging from seconds to femtoseconds, and must be: s ms us ns ps or fs
 
--precision and base represent how many decimal points of precision to use relative to the time units.

For example : `timescale 1 ns / 100 ps means
time values to be read as ns and to be rounded to the nearest 100 ps.

If timescale is omitted, there is a default time scale.

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